12-bit 80 MSPS Current Steering DAC

Features

• 90nm 6 Metal CMOS (No analog options)
• 2.5V and 1.2V power supplies required
• 80 MSPS output update rate
• Typical SFDR of 70dBc (I=5mA, R=100W)
• INL < 2LSB and DNL < 0.5LSB
• Power Dissipation
• 17.5mW
• Standby and power down modes
• Core area of 0.13mm2
• Total area of 0.18 mm2 (including reference)

Benefits

• The dynamic performance can be maintained for frequencies close to the DAC Nyquist frequency.
• The total area of the DAC including bandgap reference is 0.18mm2
• Developed on low power 90nm logic process, the DAC is ideal for integration with a DSP engine. The DAC can be ported to any similar process.
• Lower power consumption can be achieved by increasing the reference resistor size.
• The output voltage range can be set by selecting suitable load resistor or external bias resistor values. A differential output voltage swing of up to 1.5V peak to peak is possible.

Deliverables

• � Datasheet
• � Characterization Report
• � Flat Netlist (cdl)
• � Layout View (gds2)
• � Abstract View (lef)
• � Timing View (tlf)
• � Behavioral Model (VHDL/Verilog)
• � Silicon Samples
• � DemonstrationEvaluation Board
• � Integration Support

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