12-bit 80MS/s Dual-Channel ADC

Features

• SMIC 40nm Low Leakage Process (LL)
• No Analog Options
• 1.1V Core & 2.5V I/O Supplies
• 12-bit Dual-Channel High-Speed SAR ADC
• Sampling Rate: 64MS/s or 80MS/s per Channel
• Input Clock CLK: 64MHz or 80MHz
• Internal Bandgap and Biasing System Included
• All required Voltage References Included
• No External Accurate Reference required
• No External Reference Decoupling required
• Good Power-Supply Noise Rejection
• Differential Input Signal Range: 1.0Vppdiff
• Outstanding Dynamic Performance:
• 75dB SFDR
• -75dB THD
• 63.5dB SNR
• 63.1dB SNDR
• 10.2-bit ENOB
• [Noise integrated up-to Nyquist]
• Outstanding Cross-Channel Performance:
• 0.2dB Channels Gain Mismatch
• -75.0dB Crosstalk between Channels
• Idle-Mode and Power-Down Modes
• Ultra Low Power Dissipation:
• Only 12mW @ 80MS/s / 10mW @ 64MS/s
• (complete Dual-Channel ADC incl. References)
• Ultra Compact Die Area: Only 0.09mm2

Benefits

• This high-end performance is obtained with an ultra compact die area of 0.09mm2 and dissipating a mere 12mW @ 80MS/s for the complete IP.
• The S3ADSIQ80M12BSM40LLE does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioral Model (Verilog)
• Integration Support

Applications

• Connected Consumer Devices
• o 802.11ac
• o LTE
• o DVB
• o Home Network
• Wireless & Wireline Communications Infrastructure
• Wireline Communications
• Imaging

Block Diagram of the 12-bit 80MS/s Dual-Channel ADC IP Core

• see the entire 12-bit 80MS/s Dual-Channel ADC datasheet
• get in contact with 12-bit 80MS/s Dual-Channel ADC Supplier