12-bit 80MS/s Dual-Channel ultra-efficient SAR ADC

Features

• TSMC 22nm ULL Process
• No Analog Options
• 0.8V Core & 1.8V I/O Supplies
• 12-bit High-Speed SAR I/Q ADC
• Up-to 80MS/s Sampling Rate per ADC Core
• Internal Bandgap and Voltage Ref. Buffers Included
• No External Accurate Reference required
• No External Reference Decoupling required
• Differential Input Signal Range: 1.0Vppdiff
• Outstanding Dynamic Performance:
• 75.0dB SFDR
• -75.0dB THD
• 63.5dB SNR
• 63.1dB SNDR
• 10.2-bit ENOB
• [Noise integrated up-to Nyquist]
• Outstanding I/Q Cross-Channel Performance:
• < 0.2dB I/Q Channels Gain Mismatch
• -75.0dB Crosstalk between I/Q Channels
• Ultra Low Power Dissipation:
• 6mW Total with both channels @ 64MS/s each
• Ultra Compact Die Area: Only 0.043mm2

Benefits

• This high-end performance is obtained with an ultra compact die area of 0.043mm2 and dissipating a mere 6mW for the complete IP (both channels sampling at 64MS/s).
• The S3ADSIQ80M12BT22ULL does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioural Model (Verilog .v)
• Integration Guidelines and Support

Applications

• Connected Consumer Devices
• LTE
• DVB
• Home Network
• Wireless & Wireline Communications
• Imaging

Block Diagram of the 12-bit 80MS/s Dual-Channel ultra-efficient SAR ADC

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