The 12-bit Charge Redistribution DAC is especially suited to discrete-time applications, where the output signal is sampled, but also works well in continuous-time applications. The Charge Redistribution DAC has been optimized for high speed and low area. It has been designed for applications where DC transfer is not required.
This IP is silicon verified.
- Fs: max 160 MHz
- BW: 1 kHz – ½ fs
- Noise (1 kHz – 20 MHz): -72 dBV
- THD: -61 dBc
- Area: 0.1 mm2
- Baseband signal generation
- Inter-chip data communication
- Video baseband transmitting
Block Diagram of the 12-bit Charge Redistribution DAC - Fs=160MHz