The DAC is a high speed digital-to-analog converter specified to operate from a nominal 3.3V analog supply and 1.2V digital supply. On-chip calibration engine is used to reduce the non-ideal effect and improve the yield and performance. The DAC has only two external pin requirements except analog input and power supply, and it includes an internal bandgap biasing block, a digital clock management unit.
All digital interface signals are 1.2V based, providing customers flexibility to directly integrate into design core. The DAC is compact and occupies 400um x750um of die area in 65nm logic CMOS process without any mixed mode options. The fully differential architecture makes it insensitive to substrate noise coupling. Thus it is ideal as a mixed signal ASIC macro cell.
- 1. 65/55nm LL CMOS logic process without any mixed mode options.
- 2. Dual 3.3/1.2V power supplies required.
- 3. Fully integrated internal reference generator with no external pins.
- 4. 12bit resolution digital-to-analog converter.
- 5. Input clock frequency of 100MHz.
- 6. Two channels with complementary current output.
- 7. Core silicon area 400um x 750um with integrated bandgap and reference.
- 8. No MIM option necessary with logic process MOM capacitors.
- -40C to 85C operating temperature range.
- 1. No analog options
- 2. Internal reference
- 3. Compact Die Area
- 2.Flat Netlist (cdl)
- 3.Layout View (gds2)
- 4.Abstract View (lef)
- 5.Timing View (lib)
- 6.Behavioral Model (Verilog)