This design includes one sample and hold stage, one data converter, and one internal band gap reference generator. The ADC is a high speed pipelined analog-to-digital converter specified to operate from a nominal 3.3V analog supply and 1.2V digital supply. By implementing 5-stage pipelined architecture with alignment and output error correction logic, the ADC offers accurate performance and guarantees no missing codes over the full operating temperature range. This complete converter also includes a biasing block, a clock generator and an output buffer.
The ADC employs digital correction techniques to provide good differential linearity for communication applications. It can be placed into a full power down mode of operation reducing power to below 100uW, and fast wake up power down mode for less than 1us wake up time. The format of the output is unsigned binary coding.
The ADC is compact and occupies 0.5mm2 of die area in 0.13um RF CMOS process. The fully differential architecture makes it insensitive to substrate noise coupling. Thus it is ideal as a mixed signal ASIC macro cell. And all interface signals are 1.2V based, providing customers flexibility to directly integrate into design core.
- 1. High speed 12bit pipeline architecture
- 2. Integrated internal bandgap and reference generation
- 3. 3.3V analog supply and 1.2V digital supply operation
- 4. 0.13um RF CMOS technology with MIM option
- 5.Core size: 0.6mm^2
- 6.Programmable sampling frequency up to 27Msps or 54Msps
- 7.Analog input bandwidth up to 6MHz
- 8.Programmable for 10bit or 12bit operation
- 9.Low power consumption: 30mW @ 10bit, 60mW @ 12bit
- 10.Two power down control modes
- 11.Excellent DC and dynamic performances
- 12.Fast wake up time
- 13.No external component and no package pin option
- 1. Internal reference
- 2. Compact Die Area
- 2.Flat Netlist (cdl)
- 3.Layout View (gds2)
- 4.Abstract View (lef)
- 5.Timing View (lib)
- 6.Behavioral Model (Verilog)