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12-bit SAR ADC TSMC
The agileADC GP analog-to-digital converter is a configurable general-purpose ADC that uses a traditional Charge-Redistribution SAR architecture referenced to VDD, VSS. The architecture is capable of achieving up to 12-bit resolution. It includes an eight-channel input multiplexor and provides input buffers that may be bypassed for full rail-to-rail capability.
The agileADC GP analog-to-digital converter can be tuned to your specifications and is ideally suited for signal conversion and monitoring in applications such as in IoT, Security, Automotive, AI and general SoCs and ASICs.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options.
For a further product information, please contact sales@agileanalog.com
The agileADC GP analog-to-digital converter can be tuned to your specifications and is ideally suited for signal conversion and monitoring in applications such as in IoT, Security, Automotive, AI and general SoCs and ASICs.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options.
For a further product information, please contact sales@agileanalog.com
Features
- Sampling Rate options: 1 MSps;2 MSps;5 MSps;10 MSps;15 MSps;20 MSps
- Quick re-configuration to your specification
- Up to 12-bit resolution
- Up to 8 input channels
- Rail-to-rail input voltage range
- Differential / Single-Ended inputs
- Low INL and DNL (monotonic + no missing codes)
- Embedded logic with AMBA APB interface to simplify test and operation
- Integrated bandgap voltage and current reference
- Low power consumption
- Standby Mode
- Compact Die Area
- Standard CMOS process
- Operation over wide temperature range: -40C to 125C
Benefits
- Best-in-class deliverables for easy and seamless integration: our engineers have extensive experience taking complex SoCs from design to mass production
- We believe that success is not just measured by delivery of netlist and layout, rather it extends to mass-production and beyond
- Automated design procedure accelerates design time and enables quick re-centering with latest PDK updates so you can tape out with the latest foundry models
- Tried and tested architecture ensures reliability and functionality
Deliverables
- Datasheet
- Design Report
- Integration Guide
- Test Guide
- Integration model
- Tapeout Checklist
- Physical Verification Report
- Functional models
- Timing model (.LIB)
- Layout Floorplanning (LEF)
- Netlist (CDL)
- Layout (GDSII)
Applications
- IoT, Security, Automotive, AI, SoCs, ASICs
Block Diagram of the 12-bit SAR ADC TSMC IP Core
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