Low voltage differential signaling (LVDS) uses high-speed analog circuit techniques to provide multi-Giga bit data transfers on copper interconnects and is a general interface standard for high speed data transmission.
The integrated LVDSTX PHY IP provides a complete, easy-to-use SERDES solution to interface a wide variety of video host systems to flat panel displays. It supports single port or dual ports LVDS outputs to drive display with high resolution, color depth of 6/8/10 bit. To reduce EMI emission, the LVDS transmitter has incorporated Spread Spectrum control and its spread percentage can be adjusted through the internal registers.
The LVDS signal electrical specification is fully compliant with ANSI/EIA/TIA-644-1995. The design adopts HLMC55LP 1P5M logic CMOS technology.
- 1. Configurable Dual Port LVDS Transmitter PHY IP
- 2. Fully Compliant with LVDS Electrical Specification ANSI/EIA/TIA-644-1995
- 3. Digital Clock Input Supports up to 160MHz
- 4. Support Both JEIDA and VESA Bit Mapping for LVDS Signaling
- 5. Support Graphic Color Depth of 6/8/10 Bit
- 6. Low Jitter PLL Clocking
- 7. EMI Reduction Capability
- 8. Adjustable SSC Spread Percentage through the Internal Registers
- 9. Supports Internal Test Pattern(PRBS7, 1010, 1100 Pattern)
- 10. Low Power Operation
- 11. Low Stand-by Current at Power Down Mode
- 12. 1.2V and 3.3V Power Supplies Required
- 13. Size: 3.8mm2 (including core IP and all auxiliary parts: Pads, IO buffer, Debug Interface, Power rail etc.)
- 14. Aggressive ESD Protection
- The LVDS Transmitter is integrated with the PLL on chip, and also support the
- Spread Spectrum Clocking (SSC) function. The power dissipation is only 12.5mW per channel at typical case.
- 2.Characterization Report
- 3.Flat Netlist (cdl)
- 4.Layout View (gds2)
- 5.Abstract View (lef)
- 6.Timing View (tlf)
- 7.Integration Support