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12G PHY in Samsung (14nm)
The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys’ high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the Enterprise 12G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards’ electrical specifications. The PHY is small in area and provides a low-power, cost-effective solution that supports multiple industry standards to meet the needs of applications with high-speed port side, chip-to-chip, board-to-board, and backplane interfaces.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare® Physical Sublayer cores and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.These features reduce both product development cycles and the need for costly field support.
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare® Physical Sublayer cores and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.These features reduce both product development cycles and the need for costly field support.
Features
- Single, dual and quad channels
- IEEE 802.3 10G and 40G backplane (XAUI, KR & KR4), port side 40G, 100G (CR4 & CR10), and 10G (XFI, SFF-8431/SFI)
- IEEE 802.3az Electrical Energy Efficient
- SGMII, and QSGMII
- PCI-SIG PCI Express (PCIe) 3.0/2.1/1.1
- SATA 6G/3G/1.5G (Rev 3.2)
- OIF CEI-6G and CEI-11G
- CPRI, OBSAI, JESD204B
- Aggregation (x2 to x16) & bifurcation
- Auto-negotiation (AN) and optional forward error correction (FEC)
- L1 substate power management and SRIS
- Multi-tap adaptive and configurable continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
- Embedded bit error rate (BER) tester and internal eye monitor
- Built-in self test (BIST) including 7-, 9-, 11 , 15-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
- IEEE 1149.6 AC Boundary Scan
Benefits
- Support for 1.25 Gbps to 12.5 Gbps data rates
- Single, dual and quad channels
- Supports PCI Express 3.1, SATA 6G, Ethernet 40GBASE-KR4, 10GBASE-KR, 10GBASE-KX4, 1000BASE-KX, 40GBASE-CR4, 100GBASE-CR10, XFI, SFI (SFF-8431), QSGMII, and SGMII
- IEEE 802.3az Electrical Energy Efficient (EEE)
- Superior signal integrity across lossy backplanes and port side interfaces enabled by a high-performance analog front-end
- Up to 20% lower active and standby power consumption compared to competing solutions due to L1 sub-states support, novel transmitter design, DFE bypass and half-rate architecture
- Separate Refclk Independent SSC (SRIS), reference clock sharing, and on-die test features improve system design and efficiency
- Aggregation (x2 to x16) and bifurcation
- Auto-negotiation (AN) and optional forward error correction (FEC)
- L1 sub-state power management and SRIS
- Multi-tap adaptive and configurable continuous time linear equalizer (CTLE) and decision feedback equalization (DFE)
- Embedded bit error rate (BER) tester and internal eye monitor
- Built-in self-test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
- Supports IEEE 1149.6 AC Boundary Scan
Deliverables
- Verilog models
- Liberty timing views (.lib)
- LEF abstracts (.lef)
- CDL netlist (.cdl)
- GDSII
- ATPG models
- IBIS-AMI models
- HSPICE models for Tx and Rx
- Documentation
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PCI Express PHY IP
- 1-32Gbps PCI-Express Gen1 - Gen5 PHY
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- PCIe 5.0 Controller
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC