12G PHY in Samsung (14nm)
The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at speed performance. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive. The embedded BER tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare® Physical Sublayer cores and the digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.These features reduce both product development cycles and the need for costly field support.
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PCI Express PHY IP
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Gen5 PCIe Hybrid Controller with SR-IOV and ARI Support
- Gen5 PCIe Transparent Switch