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USB 4.0 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
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14-Bit 1.4MHz Bandwidth CTSD ADC
The S3ADSD3M14BT40LP is a highly-compact and ultra-low power Continuous-Time Sigma-Delta ADC with an input Signal Bandwidth of 1.4MHz.
This IP includes a first-order Anti-Aliasing filtering function. Noise Shaping is implemented with a 3rd Order Modulator. Working at 200MHz clock frequency, this ADC features an outstanding performance that includes 75.0dB Dynamic Range, 68.5dB SNR and 11.0-bit ENOB.
To allow for application flexibility whilst offering minimum area and power dissipation, this IP does not include the Digital Decimation Filter. If required, it can be included in the IP or it can, otherwise, be included externally in the SoC DSP.
This IP includes a first-order Anti-Aliasing filtering function. Noise Shaping is implemented with a 3rd Order Modulator. Working at 200MHz clock frequency, this ADC features an outstanding performance that includes 75.0dB Dynamic Range, 68.5dB SNR and 11.0-bit ENOB.
To allow for application flexibility whilst offering minimum area and power dissipation, this IP does not include the Digital Decimation Filter. If required, it can be included in the IP or it can, otherwise, be included externally in the SoC DSP.
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Block Diagram of the 14-Bit 1.4MHz Bandwidth CTSD ADC IP Core
