14-Bit 1.7MHz Bandwidth Continuous Time Sigma Delta ADC - TSMC 40nm ULP
power Continuous-Time Sigma-Delta ADC with an input
Signal Bandwidth up-to 1.7MHz.
This IP has a built-in Anti-Aliasing filtering function. Noise
Shaping is implemented with a 3rd Order Modulator.
For application flexibility, the IP includes a Reference Buffer.
Working at 200MHz clock frequency, this ADC features an
outstanding performance that includes 75.0dB Dynamic
Range, -80.0dB THD, 68.5dB SNR and 11.0-bit ENOB.
Excluding the Digital Decimation filter, this ADC power
dissipation is only uW and minimum area.
The S3ADSD3M14BT40ULPC can be cost-effectively ported
across foundries and process nodes.
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Block Diagram of the 14-Bit 1.7MHz Bandwidth Continuous Time Sigma Delta ADC - TSMC 40nm ULP
