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14-Bit 12MHz Bandwidth Continuous Time Sigma Delta ADC on UMC 40nm
With an input signal bandwidth of 12MHz, this ADC features an outstanding dynamic performance including 69.0dB
SNR, 75.0dB SFDR and 11.0-bit ENOB.
This IP includes also the Voltage Reference Buffers and the Digital Decimation Filter. The throughput rate, after decimation, is 50MS/s.
The total IP, including the References Buffers and the Decimation Filter, dissipates a total power of mW and the die area is tiny.
The S3ADSD24M14BC40LP can be cost-effectively ported across foundries and process nodes upon request.
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Block Diagram of the 14-Bit 12MHz Bandwidth Continuous Time Sigma Delta ADC on UMC 40nm

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