This customizable ADC has been designed to reduce time to market, risk and cost in the development of analog front-ends. A range of supporting IP blocks such as PLL's and reference circuits as well as companion IP blocks such as D/A converters are also available.
The ADC is a fully differential circuit, has a single-bit fourth-order cascade architecture which uses a second-order stage and two first-order stages (2-1-1) topology to achieve a fourth-order noise shaping function.
- 1.8V power supply in 0.18um CMOS process
- Input range of 1.25 Vp-p Differential
- 500 KHz Signal Bandwidth
- 1 MSPS Output Word Rate
- Dynamic Performance
- 82dB SNR at Fin=500KHz
- 84dB SFDR at Fin=500KHz
- DNL 0.5 LSB
- INL 1 LSB
- Die area of 2.0mm2
- Power Dissipation < 45mW
- Scalable to Lower Resolutions
- Part of a family of mixed signal blocks enabling it to be used as part of an analog front end.
- Area of 2.0mm2 including reference circuits.
- Developed on standard 0.18um process, which is ideal for integration with a DSP engine.
- Does not require special analog processing options.
- It has low distortion and high dynamic range so can be used in a number of demanding applications.
- Readily portable across foundries.
- Operating at 25MSPS, the ADC consumes only 45mW.
- Analog bandwidth of 500 KHz.
- Output word rate of 1 MSPS.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Silicon Samples
- DemonstrationEvaluation Board
- Integration Support