14 Bit 50 MSPS Sigma-Delta ADC

Features

• 1.8V power supply in 0.18um CMOS process
• Input range of 1.25 Vp-p Differential
• 1 MHz Signal Bandwidth
• 2 MSPS Output Word Rate
• Dynamic Performance
• 84dB SNR at Fin=1MHz
• 90dB SFDR at Fin=1MHz
• DNL 0.5 LSB
• INL 1 LSB
• Die area of 2.0mm2
• Power Dissipation < 80mW
• Scalable to Lower Resolutions

Benefits

• Part of a family of mixed signal blocks enabling it to be used as part of an analog front end.
• Area of 2.0mm2 including reference circuits.
• Developed on standard 0.18�m process, which is ideal for integration with a DSP engine.
• Does not require special analog processing options.
• It has low distortion and high dynamic range so can be used in a number of demanding applications.
• Readily portable across foundries.
• Operating at 50MSPS, the ADC consumes 80mW.
• Analog bandwidth of 1 MHz.
• Output word rate of 2 MSPS.
• In low power mode (40mW) the ADC can operate up to 25MSPS

Deliverables

• The S3AD50M14BC18 is available from S3 under license agreement and supported with the following deliverables:
• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (tlf)
• Behavioral Model (VHDL/Verilog)
• Silicon Samples
• DemonstrationEvaluation Board
• Integration Support
• For more detailed information regarding the S3AD50M14BC18 A/D converter please refer to the full datasheet which is available upon request. The S3AD50M14BC18 can be delivered as a single IP component for customer integration or S3 engineers can integrate it as part of a SoC engagement.

• see the entire 14 Bit 50 MSPS Sigma-Delta ADC datasheet
• get in contact with 14 Bit 50 MSPS Sigma-Delta ADC Supplier