14-Bit 800MS/s Wide-Band Current Steering DAC
It uses 6 linear bits and 8 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output.
This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
Considering an input signal frequency of 85MHz sampling at 800MS/s the resultant SNDR > 70dB and an SFDR > 63dBc.
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Block Diagram of the 14-Bit 800MS/s Wide-Band Current Steering DAC
