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14-Bit 800MS/s Wide-Band Current Steering DAC
The S3DA800M14BT65G employs a current steering architecture with differential current outputs.
It uses 6 linear bits and 8 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output.
This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
Considering an input signal frequency of 85MHz sampling at 800MS/s the resultant SNDR > 70dB and an SFDR > 63dBc.
It uses 6 linear bits and 8 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output.
This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
Considering an input signal frequency of 85MHz sampling at 800MS/s the resultant SNDR > 70dB and an SFDR > 63dBc.
Features
- 65nm TSMC Logic G Process, 6 Metals Used (No Analog Options)
- 1.8V and 1.0V Supplies
- Sampling Rate up to 800MS/s
- 1.0Vpp Differential Output Range
- DNL< 0.8LSB; INL< 3.0LSB.
- Performance for Fout<85MHz
- SNR >73dB, SFDR > 63dBc,ENOB>10.5bits
- IM3>-68dBc @70MHz
- Stand-By and Power-Down Modes
- Compact Die Area: 0.4mm2
Benefits
- The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (SystemVerilog)
- Integration Support
Applications
- Wireless Communication
- DOCSIS 3.0
- Wireline communications
Block Diagram of the 14-Bit 800MS/s Wide-Band Current Steering DAC
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