16-bit 100dB SNDR Sigma-Delta ADC - GlobalFoundries 65nm
The architecture employs a mixed Clock- Boosting/Switched-Opamp second-order SD modulator. A chopping technique is employed to reduce noise.
The block includes a Sinc decimation filter. The output data rate is set to 122Hz, with valid conversions available every 8.2ms. The filter can be customized to meet different customer’s requirements.
The design is implemented with Deep N-Well to improve substrate isolation.
The 16-bit Sigma-Delta ADC can be cost-effectively ported across foundries and process nodes upon request.
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Block Diagram of the 16-bit 100dB SNDR Sigma-Delta ADC - GlobalFoundries 65nm
