Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
16 bit, 5 Msps DAC
The DAC uses a proprietary architecture that guarantees monotonicity. It also features low glitch, low drift, small area and low power consumption. VSENSE pin is provided to set the load voltage with high accuracy. Both VOUT and VSENSE pins must be routed to the load.
The DAC’s 16-bit parallel interface can be updated at up to 5 MHz on the CLKIN rising edge. When EN_DAC pin is low, the DAC enters a power down mode, where both VOUT and VSENSE pins become high impedance. DAC becomes active when the EN_DAC pin is high.
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