This macro-cell is a single-channel 16-bit oversampling ADC intended for digital audio bandwidth applications. Supplied with 1.2V, the analog and the digital supply is kept separate in order to decrease noise. A master clock has to be provided at a frequency of 128 x Fs. The use of a differential input signal provides increased dynamic range and excellent power supply rejection characteristics. Never¬theless, a single-ended input can also be applied to the ADC by shortcircuiting one input to ground.
blocks for RESET and Power-Down are also present.
The digital part consists basically of a triple-stage Finite-Impulse-Response Decimation Filter required for down sampling and lowpass filtering
data coming from the Sigma-Delta modulator, preserving linear-phase. The output data is a digital stream with a clock frequency of 16 x Fs (16 x 48 KHz)..
- Single-channel Sigma Delta ADC
- Fourth-order single-loop full feedforward Sigma-Delta modulator
- 16-bit resolution
- 48 kHz sampling frequency
- 128 oversampling ratio
- 600 mVpp differential input dynamic range
- Signal bandwith up to 20 kHz
- 6.144 MHz (external) clock
- Internal reference and bias circuitry
- Reset function
- Power down mode
- Matlab Model
- GDSII Layout Database
- Assembly Guidelines and Full Integration support