16 Bit Sigma Delta ADC
The digital part consists basically of a triple-stage Finite-Impulse-Response Decimation Filter required for down sampling and lowpass filtering data coming from the Sigma-Delta modulator, preserving linear-phase. This filter will effectively remove the modulator’s high frequency quantization noise. The output data is a digital stream with a clock frequency of 16 x Fs (16 x 48 KHz)..
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