This macro-cell is a single-channel 16-bit oversampling ADC intended for digital audio bandwidth applications. Supplied with 1.2V, the analog and the digital supply is kept separate in order to decrease noise. A master clock has to be provided at a frequency of 128 x Fs. The use of a differential input signal provides increased dynamic range and excellent power supply rejection characteristics. Never¬theless, a single-ended input can also be applied to the ADC by shortcircuiting one input to ground. The analog part of the ADC is split into different main blocks, a biasing block, the Sigma-Delta Modulator core, that consists of a fourth-order full feedforward topology with a one-bit noise shaping quantizer and a clock generator block. Minor additional blocks for RESET and Power-Down are also present.
The digital part consists basically of a triple-stage Finite-Impulse-Response Decimation Filter required for down sampling and lowpass filtering data coming from the Sigma-Delta modulator, preserving linear-phase. This filter will effectively remove the modulator’s high frequency quantization noise. The output data is a digital stream with a clock frequency of 16 x Fs (16 x 48 KHz)..