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16-Bit Sigma-Delta Stereo Audio CODEC with Microphone and Headphone, Fujitsu 65nm
The AR34F5B specifies a very low power stereo audio CODEC IP for multimedia audio system. The IP employs multibit sigma delta architecture. It includes built-in bandgap reference and on-chip regulators for better noise immunity. The IP is fabricated in Fujitsu 65nm process and can be ported to other 65nm or 55nm processes.
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Sigma Delta IP
- 16 Bit 10 kS/s Incremental Delta - Sigma ADC
- 400MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
- 800MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
- 14-Bit 20MHz Bandwidth Continuous Time Sigma Delta ADC
- 80MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
- 14-Bit 1.7MHz Bandwidth Continuous Time Sigma Delta ADC