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16G Multi-protocol SerDes PHY
Designed to maximize interface speed with broad protocol compatibility speed in the difficult system environments found in enterprise-class applications.
The Rambus 16G Multi-Protocol SerDes (MPS) are a complete solution designed with a system-oriented approach to maximize flexibility and ease integration for our customers. They are optimized for power and area in difficult, highloss channels and utilizes FIR, CTLE, and DFE equalizers to recover data in the presence of channel and system interfaces. Our 16G SerDes PHYs are designed with a minimal set of broadside control and status pins, as well as a softconfigurable PCS, to support a wide range of applications including:
• Gigabit Ethernet copper backplane networking
• XFP and SFP+ optical modules
• System packet interfaces
• Hybrid Memory Cube
• TDM Fabric to Framer interface
• Graphics cards
• PCIe peripheral connectivity
• Server connectivity
The Rambus 16G Multi-Protocol SerDes (MPS) are a complete solution designed with a system-oriented approach to maximize flexibility and ease integration for our customers. They are optimized for power and area in difficult, highloss channels and utilizes FIR, CTLE, and DFE equalizers to recover data in the presence of channel and system interfaces. Our 16G SerDes PHYs are designed with a minimal set of broadside control and status pins, as well as a softconfigurable PCS, to support a wide range of applications including:
• Gigabit Ethernet copper backplane networking
• XFP and SFP+ optical modules
• System packet interfaces
• Hybrid Memory Cube
• TDM Fabric to Framer interface
• Graphics cards
• PCIe peripheral connectivity
• Server connectivity
Features
- PMA hard macro optimized for PCIe, SATA, 10G/CEI/Interlaken, HMC, Fibre Channel & JESD204 interfaces
- PCS soft macro for PCIe (PIPE4.2 compliant) and 10G-KR connectivity to controller macro
- x1, x2, x4, and x8-lane configurations
- BIST with PRBS generator and checker
- Tx and Rx equalization
- Data rate negotiation
- Equalization adaptation
- Available for the TSMC, Global Foundry, and Samsung process node
Benefits
- Duplex lane configurations of x1, x2, x4, and x8
- Transmit swing of at least 800 mV differential peak-to-peak for MR & LR, 360mv for SR
- Support for AC-coupled interfaces
- Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
- BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and GbE protocols
- A wide range of PLL multiplication options supporting low reference clock frequencies
- Flexible ASIC clocking
- Tight skew control of 2UI between lanes of the PMA
- 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- Deterministic latency with in +-1UI variation for Tx lane
- Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
- 6-tap Rx DFE (decision feedback equalizer)
- Second-order CDR meeting SSC and RX sinusoidal jitter requirements
- Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
- Built-in Self Test (BIST) with ATPG and AC/DC Boundary scan support
- Built-in PRBS pattern generation and checking for standalone loopback testing
- In-situ real-time monitoring and receive data eye schmoo
- Operation across a wide temperature range (-40 C to +125 )
Deliverables
- PMA Hard Macro
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- PCS-BIST Soft Macro
- RTL model
- Datasheet
- SoC integration guide
- Optional design integration
- and bring-up support services
Applications
- Enterprise, High-Performance Computing
Block Diagram of the 16G Multi-protocol SerDes PHY IP Core
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