16G Multi-protocol SerDes PHY

Features

• Duplex lane configurations of x2, x4, and x39
• Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
• Support for AC-coupled interfaces
• Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
• BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and Gbe protocolsA wide range of PLL multiplication supporting low reference clock frequenciesTight skew control of 2UI between lanes of the PMABuilt-in Self Test (BIST) with ATPG and AC/DC boundary scan supportBuilt-in PRBS pattern generation and checking for standalone loopback testingContinuous time linear equalizer (CTLe) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies

Benefits

• Duplex lane configurations of x1, x2, x4, and x8
• Transmit swing of at least 800 mV differential peak-to-peak for MR & LR, 360mv for SR
• Support for AC-coupled interfaces
• Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
• BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and GbE protocols
• A wide range of PLL multiplication options supporting low reference clock frequencies
• Flexible ASIC clocking
• Tight skew control of 2UI between lanes of the PMA
• 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
• Deterministic latency with in +-1UI variation for Tx lane
• Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
• 6-tap Rx DFE (decision feedback equalizer)
• Second-order CDR meeting SSC and RX sinusoidal jitter requirements
• Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
• Built-in Self Test (BIST) with ATPG and AC/DC Boundary scan support
• Built-in PRBS pattern generation and checking for standalone loopback testing
• In-situ real-time monitoring and receive data eye schmoo
• Operation across a wide temperature range (-40 C to +125 )

Deliverables

• PMA Hard Macro
• PCS-BIST Soft Macro
• Datasheet
• SoC integration guide
• Optional design integration and bring-up support services

Applications

• Automotive,Communications,Consumer Electronics,Data Processing,Industrial and Medical,Military/Civil Aerospace,Others

Block Diagram of the 16G Multi-protocol SerDes PHY IP Core

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