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PVT Controller (Series 5) (Sub-system for complete PVT monitoring), TSMC N4P
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16G UCIe Advanced PHY for TSMC 3nm
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity
The Cadence® UCIe IP complete solution meets the growing demand for high performance and bandwidth, superior power efficiency, and ultra-low latency interconnect between dies on different foundries and process nodes. The Cadence® 16G UCIe PHY provides an industry chiplet interoperable solution for on-die integration, as it caters to growing system-in-package (SiP) applications. Standard and advanced UCIe PHY options offer flexibility for designers in implementing a wide range of packaging options. The UCIe PHY IP employs Known Good Die (KGD) techniques and is engineered to quickly and easily integrate into any system-in-package (SiP). It is verified with the UCIe Controller IP as part of a complete UCIe subsystem solution, which also includes Cadence UCIe Verification IP (VIP). The Cadence UCIe total solution offers ease of integration of both the PHY and controller IP in an open chiplet ecosystem.
The Cadence® UCIe IP complete solution meets the growing demand for high performance and bandwidth, superior power efficiency, and ultra-low latency interconnect between dies on different foundries and process nodes. The Cadence® 16G UCIe PHY provides an industry chiplet interoperable solution for on-die integration, as it caters to growing system-in-package (SiP) applications. Standard and advanced UCIe PHY options offer flexibility for designers in implementing a wide range of packaging options. The UCIe PHY IP employs Known Good Die (KGD) techniques and is engineered to quickly and easily integrate into any system-in-package (SiP). It is verified with the UCIe Controller IP as part of a complete UCIe subsystem solution, which also includes Cadence UCIe Verification IP (VIP). The Cadence UCIe total solution offers ease of integration of both the PHY and controller IP in an open chiplet ecosystem.
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