16nm LVCMOS Bidirectional IO
Features
- Implemented in TSMC 16FFC process
- Uses SVT,LVT devices for operation under both core and IO supply
- Intended for flip-chip packages
- Compatible with both IEEE General Purpose LVDS
- Powered from 1.8V +/- 7.5% IO supply and 0.8V +/- 10% or 1.0V -10% & +5% Core supply
- Operates in junction temperature ranges from -40 to 125 degree Celsius
- No power supply sequencing restrictions
- ESD immunity of 2KV HBM, 250V (5A) CDM and +/- 100mA current injection for latch up
Deliverables
- Specifications
- GDSII
- LEF file
- LVS netlist
- Verilog Model
- Timing Model
- Documentation
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