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16nm LVDS Receiver IO
Sankalp Semiconductor offers SSLVDS_IO_RXT016FFC general purpose IOs targeted for TSMC 16nm FFC process (with 7-2-2 Metal Stack). It uses LVT, SVT thin-oxide 1.0V and 1.8V transistors, there is no deep Nwell requirement. It operates on a core supply of 0.8 /1.0 V and I/O supply 1.8 V.
Features
- Implemented in TSMC 16nm FFC CMOS process using 7-2-2 Metal Stack
- Uses LVT, SVT core and 1.8V SVT transistors.
- Targeted for flip-chip packages
- Compatible with ANSI/TIA/EIA-644-A-2001 LVDS Standard
- Compatible with IEEE 1596.3-1996 Standard for LVDS Scalable Coherent Interface
- Powered from 1.8V +/- 7.5% IO supply and 0.8V +/- 10% or 1.0V -10% & +5% Core supply
- Operates in junction temperature ranges from -40 to 125 degree Celsius
- No power supply sequence restrictions
Deliverables
- Specifications
- GDSII
- LEF file
- LVS netlist
- Verilog Model
- Timing Model
- Documentation
View 16nm LVDS Receiver IO full description to...
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16nm
- USB 3.1 PHY (10G/5G) - TSMC 16FFC x1 OTG, North/South Poly Orientation
- MIPI D-PHY 2.0Gbps (4-lanes TX/RX, PLL integrated) TSMC 16FF+LL
- MIPI D-PHY 2.0Gbps (4-lanes RX) TSMC 16FF+LL
- MIPI D-PHY 2.0Gbps (4-lanes TX, PLL integrated) TSMC 16FF+LL
- TSMC CLN16FF+LL 16nm Ultra PLL - 15MHz-3250MHz
- Free-running on-chip oscillator
