MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
18-bit Sigma Delta Stereo Audio 28nm silicon proven in TSMC 28HPC ADC
The device is fabricated on TSMC 28HPC process
where high speed precision analog circuits are
combined with high density logic circuits.
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ADC/DAC IP
- Audio codec with capacitor-less 106 dB dynamic range ADC and 120 dB SNR DAC with low latency
- 12-bit 12-Gsps Transceiver (ADC/DAC/PLL)
- 8-bit 48-Gsps Transceiver (ADC/DAC/DLL)
- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
- Analog Front End: 4 channels of 12-bit 2 GSPS ADC IQ Pairs, 4 channels of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL
- Analog Front End: 1 channel of 12-bit 2 GSPS ADC IQ Pairs, 1 channel of 12-bit 2 GSPS DAC IQ Pairs, PVT & Integrated PLL