Packet Architects offers a series of high speed switching IP cores, developed using the unique FlexSwitch toolchain. This toolchain provides a fast and flexible development environment for switching/routing IP cores for any packet based technology.
This Ethernet Switch IP core offers a full range of features and wirespeed throughput on all ports, one of which can be configured as a high speed CPU port. Each port has a number of priority queues controlled by a strict priority scheduler. This allows the most timing critical packets to get minimal delay while providing fairness between queues.
The switch is built around a shared buffer memory architecture supporting wirespeed switching on all ports without head of line blocking. It offers dynamic allocation of packet buffering per port and priority to avoid starvation due to over-allocation. The switching core also features multiple VLAN tagging and untagging operations, along with egress VLAN translation.
A processor interface allows setup of tables and registers. There is also a packet-based CPU port for packets to and from the CPU.
This IP core requires no software setup, and it has hardware learning for MAC addresses. Thus it is ready to receive and forward Ethernet frames immediately once powered up.
- Switch throughput depends on technology and features, but 64 gigabit ports is a push-button implementation process in mainstream FPGA technology.
- Integrates seamless with Open Cores, Xilinx and Altera 1GE and 10GE MACs.
- Dedicated port for packets to / from CPU.
- To-CPU tag identifies reason for slow-path processing
- From-CPU tag for bypassing ingress packet processing
- MAC based protection of packets to CPU
- Full wirespeed on all ports and for all Ethernet frame sizes.
- Store and Forward shared memory architecture
- Support for Jumbo frame packets of any size
- Input and Output mirroring.
- L2 MAC table of any size, hash based 4-way with optional hash collision CAM and support for static entries.
- 0 to 4K VLAN table
- VLAN operations supported are push, pop, swap, up to three operations per packet and operations can be done at ingress, vlan and egress.
- 0 to 32K L2 multicast table.
- Hardware based automatic aging and wire-speed learning of L2 addresses.
- Strict Priority Scheduler with 1-16 priority queues per egress port.
- Flexible mapping of 802.1q, MPLS Exp, IPv4/IPv6 TOS byte to egress queue priority.
- Spanning tree & Multiple spanning tree support with flexible handling of BPDU frames.
- Buffer Memory Resource counters with configurable limits per egress port and queue.
- Drop counters for packets dropped due to resource limits.
- CPU interface for accessing registers and tables in the core. Supporting multiple outstanding transactions for high speed access.
- Queue management: disable queueing, disable scheduling, drain queue, redirect port.
- Multicast/Broadcast storm control based on packets or bytes per port.
- Source MAC and Destination MAC range filtering with actions for drop, send to CPU, send to port and assign queue priority
- Ingress and Egress packet type filtering
- Unicast & Multicast IPv4,IPv6 filtering
- MPLS packet filtering
- Single or dual tagged packet filtering
- Broadcast packet filtering
- Flooded packet filtering
- Multiple ACL lookups per packet based on SA MAC, DA MAC,customer VLAN, service VLAN, L3 Protocol, L3 SA, L3 SA, L4 Protocol, L4 Source and Destination ports,
- Actions for ACL are drop, send to CPU, send to port, assign a new egress queue priority
- Quick customization thanks to HLS-based packet processing, and a generated datapath.
- Verilog 2001 source code of IP core.
- Datasheet of registers & theory of operations..
- Easy to parse YML file for register mapping.
- A simple verilog testbench