Comcores Ethernet Switch IP core is a highly configurable and size optimized implementation of a non-blocking crossbar switch that allows continuous transfers between up to four (4) 10 Gbps Ethernet XGMII ports and fourty (40) 1 Gbps GMII interfaces.
The switch supports MAC learning, VLAN 802.1Q, multicast, broadcast as well as 1588 transparency. It implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking.
Each port provides GMII or XGMII native interfaces for Ethernet PHY devices. The number of ports within the switching fabric is configurable at compile time.
- Delivers Performance
- Automatic MAC addresses learning and aging
- Programmable firmware operation with Static or Dynamic (Learning) switching tables
- Full duplex Ethernet interfaces
- Easy to use
- XGMII/ GMII interfaces for attaching to external Physical Layer devices (PHY)
- Very easy integration with standard Xilinx AXI4 Lite control interface
- Can be used in managed or unmanaged implementations
- Highly Configurable
- Up to 40 1G and 4 10G ports configurable at compile time
- Configurable queuing behavior (round-robin, fair queuing, etc.)
- Support Ethernet Multicast, Broadcast with flooding control to avoid unnecessary duplication of frames
- Silicon Agnostic
- Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs
- The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.
- Cloud RAN:
- Use this switch to ensure smallest size switch for switching of header information in a CPRI cross connect scenario.
Block Diagram of the 1G/10G Ethernet Switch IP Core