1G/10Gb Ethernet PHY

Features

• Integrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMAIntegrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMA
• Direct internal interface with Altera 1G/10GbE (10M-10GbE) MAC for a complete single-chip solution
• User selectable 1G/10Gb data rates during run-time or automatic speed detection (parallel-detect) between 1Gb and 10Gb and reconfiguration by PHY IP, or data rate selection among 10/100/1000Mb with Ethernet auto-negotiation function
• 10Gb, 1G/10GbE and 10M-10GbE (SGMII/1G/10GbE) options
• IEEE 1588 v2 option
• Synchronous Ethernet (Sync-E) option
• Serial transceiver clock and data recovery (CDR) recovered clock output signal exposed to the FPGA fabric for routing to a Sync-E jitter cleaner PLL
• Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input
• Receiver-link fault status detection
• Local serial loop-back from transmitter to receiver at serial transceiver for self test
• High-performance internal system interfaces
• GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE (10M-10GbE) MAC, 8 bits at 125 MHz and 72 bits at 156.25 MHz respectively for data transfer
• Altera Avalon® Memory-Mapped (Avalon-MM) 32 bit interface for slave management

Benefits

• SOPC Builder Ready: No
• Qsys Compliant: No

• see the entire 1G/10Gb Ethernet PHY datasheet
• get in contact with 1G/10Gb Ethernet PHY Supplier