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1G Ethernet Switch
Comcores Lite Ethernet Switch (LES) IP core is a highly configurable and size optimized implementation of a non-blocking crossbar switch that allows continuous transfers between up to 36 ports Ethernet ports via 1 Gbps GMII interfaces.
The switch supports MAC learning and implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking.
The switch supports up to 36 ports where each port provides GMII native interface for Ethernet PHY devices. The number of ports are configurable at compile time.
Comcores Lite Ethernet Switch (LES) IP core is a silicon agnostic implementation targeting any ASIC, FPGA or ASSP technologies.
The switch supports MAC learning and implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking.
The switch supports up to 36 ports where each port provides GMII native interface for Ethernet PHY devices. The number of ports are configurable at compile time.
Comcores Lite Ethernet Switch (LES) IP core is a silicon agnostic implementation targeting any ASIC, FPGA or ASSP technologies.
Features
- Delivers Performance
- Automatic MAC address learning
- Programmable firmware operation with Static or Dynamic (Learning) switching tables
- Full duplex Ethernet interfaces
- Highly Configurable
- Up to 36 ports configurable at compile time
- Configurable queuing behavior (round-robin, fair queuing, etc.)
- Supports Ethernet Multicast, Broadcast with flooding control to avoid unnecessary duplication of frames
- Easy to use
- Very easy integration with standard Xilinx AXI4 Lite control interface
- GMII interfaces for attaching to an external Physical Layer device (PHY)
- Can be used in managed or unmanaged implementations
- Silicon Agnostic
- Designed in VHDL-93 and targeting any RTL implementation, such as ASICs, ASSPs and FPGAs.
Benefits
- Silicon Agnostic
- Ultra Compact Size
- Hardware proven
- Modular design with no performance limitations
- Smallest size Ethernet Switch available
- Optimal balance between IP-size and maximum data throughput rate can be configured
Deliverables
- RTL is delivered as VHDL-93 sources
- User Manual describing among others top Level I/O’s definition, registers, clocking strategy, functional description
- Basic Functional test bed for loopback tests and other sanity checks
- Hardware Demonstrator Platform based on Xilinx VC709
Applications
- C-RAN Switching
- Test Equipment Applications
- Industrial networks
Block Diagram of the 1G Ethernet Switch IP Core
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