To efficient transfer large amount of data and off-load the system processor, BitSim has launched its IP, Bit-UDP Ethernet.
This core is a real-time offload engine where the communication is accelerated in the FPGA, with more than ~900+ Mb/s of effective data transfer rate.
- Receives and sends UPD-packets over Ethernet
- Supports 10, 100 and 1 000 Mb/s (1 Gb/s) transfer rates
- ARP-table, no of entries can be selected
- Programmable Source/Destination ports and IP/MAC/Default gateway address
- Works with standard Ethernet transceivers using (G)MII-interface
- RGMII optional
- The IP can be used with or without AXI4-Stream
- Loopback before or after AXI-level possible, for debug purposes
- Prepared and support for SyncE, including ESMC protocol
- Implemented as general VHDL code, independent of FPGA vendor
- Encrypted or readable source code
- VHDL test benches and scripts
- HW-platform/reference kit available
Block Diagram of the 1G IP/UDP full HW Stack Transmitter / Receiver