MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive
2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
AresCORE16 can be configured to support advanced packaging such as CoWoS (Chip-on-Wafer-on-Substrate), InFO (Integrated-Fan-Out) for maximum density, and Organic Substrates for most cost-effective solution covering all market segments.
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Block Diagram of the 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
SerDes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency