The interface to the core logic includes differential signal pins (INP and INN) to transmit data, and two control pins (OEN and EN) to configure the state of the transmitter. There are other two internal pins (VREF and IREF) to get voltage reference and current reference. OUTP and OUTN are complementary outputs to connect to the bonding pads. LVDS transceiver cell may be used for half-duplex data transmission. In this case, input OEN controls the direction of the transmission. When OEN = 1, block operates in the receiver mode – the transmitter output is in high impedance state. When OEN = 0, block operates in the transmitter mode. In this case, the transmitter drives its output current into the differential LVDS line, with the polarity corresponding to the bit value being transmitted. This LVDS driver provides a high current mode
(IREF equal 20 uA or 19 uA) for system designs that employ double termination (near-end and far-end) of the differential signaling lines. The low current drive mode (IREF equal 10 uA or 9.5 uA) is sufficient for typical single ended termination at the receiver.