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2.5 Gbit/s Framing/Overhead Processing/RS(255,239)
The Xelic Optical Transport Network (OTN) Framer Core (XCO1) performs Optical Channel Transport Unit (OTU), Optical Channel Data Unit (ODU), and Optical Channel Payload Unit (OPU) overhead processing, aligns incoming OTU or ODU frames, and provides overhead interpretation with error detection and performance monitoring. The XCO1 contains independent transmit and receive processors with external ports for overhead insertion and extraction. External ports are provided for optional EFEC processing. System side data is transferred at a nominal rate of 2.488Gb/s using a 32-bit data bus operating at 77.76Mb/s. Line side data is transferred at an OTU1 rate using a 32-bit data bus operating at 83.31Mb/s or at an ODU1 rate using a 32-bit data bus operating at 78.09Mb/s.
The XCO1 Transmit Processor inserts OTU1, ODU1, and OPU1 overhead, calculates and inserts parity, automatically generates Backward Defect Indication (BDI) signaling, and scrambles generated frames. Support is provided for up to 6 levels of tandem connection overhead insertion. Programmable Trail Trace Identifier buffers are implemented for Section Monitoring (SM), Path Monitoring (PM), and Tandem Connection Monitoring overhead insertion. Diagnostics support includes optional corruption of inserted parity, corruption of scrambling, frame alignment signal corruption, and maintenance signal insertion. Programmable payload support includes asynchronous CBR25G, bit synchronous CBR25G, ATM, GFP, null test, and PRBS mapping types. Forward Error Correction (FEC) encoding is provided for generated OTU1 frames using Reed Solomon RS(255,239) 16 byte interleaved codes. ODU1 frames are optionally generated through programmable register control.
The XCO1 Receive Processor contains a configurable frame alignment unit with programmable options for OOF/OOM and LOF/LOM algorithm state transitions. Incoming OTU or ODU frames are descrambled (optional) and aligned for OTN overhead processing. OTU, ODU, and OPU overhead information is extracted to both internal register locations and an external overhead port. Frame alignment signal overhead is interpreted to detect and report various conditions which include OOF, LOF, LOA, OOM, LOM, and LOMA. OTU AIS, ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals are detected with optional interrupt generation. OPU payload type mismatch error conditions are detected and support is provided for programmable payload type accept and inconsistent thresholds.
Performance counters (configurable for bit or block count type) are provided for the accumulation of inserted (XCO1 transmit processor) and detected (XCO1 receive processor) positive and negative justification events along with BIP-8 parity and BEI errors for OTU SM, ODU TCMi, and ODU PM (XCO1 receive processor). Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCO1 provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
The XCO1 Transmit Processor inserts OTU1, ODU1, and OPU1 overhead, calculates and inserts parity, automatically generates Backward Defect Indication (BDI) signaling, and scrambles generated frames. Support is provided for up to 6 levels of tandem connection overhead insertion. Programmable Trail Trace Identifier buffers are implemented for Section Monitoring (SM), Path Monitoring (PM), and Tandem Connection Monitoring overhead insertion. Diagnostics support includes optional corruption of inserted parity, corruption of scrambling, frame alignment signal corruption, and maintenance signal insertion. Programmable payload support includes asynchronous CBR25G, bit synchronous CBR25G, ATM, GFP, null test, and PRBS mapping types. Forward Error Correction (FEC) encoding is provided for generated OTU1 frames using Reed Solomon RS(255,239) 16 byte interleaved codes. ODU1 frames are optionally generated through programmable register control.
The XCO1 Receive Processor contains a configurable frame alignment unit with programmable options for OOF/OOM and LOF/LOM algorithm state transitions. Incoming OTU or ODU frames are descrambled (optional) and aligned for OTN overhead processing. OTU, ODU, and OPU overhead information is extracted to both internal register locations and an external overhead port. Frame alignment signal overhead is interpreted to detect and report various conditions which include OOF, LOF, LOA, OOM, LOM, and LOMA. OTU AIS, ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals are detected with optional interrupt generation. OPU payload type mismatch error conditions are detected and support is provided for programmable payload type accept and inconsistent thresholds.
Performance counters (configurable for bit or block count type) are provided for the accumulation of inserted (XCO1 transmit processor) and detected (XCO1 receive processor) positive and negative justification events along with BIP-8 parity and BEI errors for OTU SM, ODU TCMi, and ODU PM (XCO1 receive processor). Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCO1 provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
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