The Xelic OTN 2.5Gb/s FEC Decoder (XCO1FECD) core detects and corrects incoming errors using interleaved Reed Solomon (255,239) codes for Optical Transport Network applications. Interleaving is performed as outlined in specification G.709 with FEC codewords containing 255 byte symbols made up of 239 byte data symbols and 16 byte check symbols. The XCO1FECD can be parameterized to support 16, 32, or 64 bit data widths.
The XCO1FECD accepts incoming data for interleaving and FEC decoding. Interleaving is performed by dividing 3824 bytes from each row of the ODUk frame structure into 16 sub-rows prior to FEC decoding. The XCO1FECD contains m independent instances of Reed Solomon (255,239) decoders, where m is the data bus width size option of the core chosen in bytes to decode the sixteen byte-interleaved sub-rows of data. Interleaved frames are interpreted with correctable and uncorrectable errors identified and accumulated in dedicated counters. The decoder algorithm implemented allows for correction of up to sixteen errors per codeword or 512 erroneous bytes per frame. If more than sixteen errors are detected, the codeword is marked as invalid. A de-interleaving stage follows FEC decoding to organize outgoing data into the proper format while performance counters are being updated.
An integrated FEC Signal Degrade block accumulates bit-errors over a fixed frame-based time interval and compares it to one of two configurable threshold constants. The XCO1FECD core supports normal, sleep, and bypass modes of operation. Saturating performance counters are provided for the accumulation of correctable symbols, correctable 0’s, correctable 1’s, and uncorrectable codewords.