USB V3.1 Power Delivery Type-C Port Evaluation board for OTI9108 IP
2.5Gbps Ethernet PCS IP Core
The two major non-compliances are data rate (2.5 Gbps instead of 1 Gbps) and GMII data bus width (16 bits instead of 8 bits).
This PCS IP core was specifically developed to operate with the Lattice 2.5 Gbps MAC IP core. The Lattice 2.5G PCS and MAC IP cores are 100% compatible and can be used to create a full PHY/MAC Ethernet data path that operates at 2.5 Gbps.
This document describes the 2.5 Gbps Ethernet PCS IP core’s operation, and provides instructions for generating the core through the Lattice IPexpress™ tool, and for instantiating, synthesizing, and simulating the core.
The 2.5 Gbps Ethernet PCS IP core converts GMII frames into 8-bit code groups in both transmit and receive directions and performs auto-negotiation with a link partner as described in IEEE 802.3z specification.
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Block Diagram of the 2.5Gbps Ethernet PCS IP Core IP Core
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