The SVRPlus supports a clock lane and 4 data lanes,
each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
The highly parallel architecture of the SVRPlus2500 allows
relatively slow internal clocks of approximately 160Mhz.
The SVRPlus2500 supports all CSI2 mandatory and optional video formats,
including compressed video formats. Noise resiliency is improved using Pseudo-Random-Binary
Sequence (PRBS) encoding on the data lanes.
The SVRPlus2500 complies with MIPI CSI2 and DPHY specifications (version 2.0 of both documents).
The SVRPlus2500 receives a single clock lane and four data lanes, complying with MIPI DPHY 2.0,
at up to 2.5Gbps per lane. The DPHY input data is converted to parallel lanes by FPGA-specific
high-speed 1:16 DESERS. The data comprises CSI2 2.0 short, long and calibration packets.
The SVRPlus2500 decodes and outputs the received pixels, at 4,8 or 16 parallel pixels.
Line error information can be read from on-IP registers, inducing BER measurements