The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of the SVTPlus2500 allows relatively slow internal clocks of approximately 160Mhz. The SVTPlus supports all CSI2 mandatory and optional video formats, including compressed video formats. Noise resiliency is improved using Pseudo-Random-BinarySequence (PRBS) encoding on the data lanes.
The SVTPlus-CSI2-F complies with MIPI CSI2 and DPHY specifications (version 2.0 of both documents).
The SVTPlus2500 receives parallel pixels from a video source (1,2,4 or 8 pixels per clock). The pixels are translated to MIPI CSI2 packets and output from the SVTPlus2500 by high-speed parallel and low-power signals. The high-speed parallel signals are converted by an FPGA-specific high-speed 16:1 seriallizer, to DPHY high-speed signals, at up to 2.5Gbps per lane. An external LVDS to DPHY device converts the high speed and the low-power inputs to DPHY signals, transmitted over a single clock lane and up to four data lanes. A simple CPU is typically required for configuration and, if needed, for diagnostics.