This IAMP has been designed for use as a low noise, programmable gain current amplifier for the G.Fast DSL protocol standard.
The IAMP has a gain range of -24dB to +1dB. At the 0dB setting the IAMP provides a nominal power of 4dBm into a 100Ω terminated line via a centre-tapped 1:1.25 transformer (centre tap at 3.3V) with a near-end termination resistance of 73.2Ω. In this case the output voltage swing at each of the differential output pins of the IAMP is between 1.9V and 4.7V
For good linearity the IAMP is biased with a DC standing current to ensure that the IAMP mirror transistors do not turn off at maximum signal excursions. The value of this standing current can be programmed to allow a trade-off of power and linearity.
The IAMP supports a “soft-start” mechanism to eliminate any transients when activating/de-activating it due to the large current drawn by the IAMP.
This block has a narrowband and wideband power mode.
- TSMC 40nm LP CMOS process
- Bandwidth selectable up to 210MHz
- Fully differential architecture for noise immunity
- Distortion-limited MTPR : 55dB (@ 4dBm output, Narrow Band Mode)
- Noise-limited MTPR: 69dB (@ 4dBm output, Narrow Band Mode)
- Gain range: -20 to +4dBm (1dB gain step)
- Low Power Dissipation
- Compact Die Area
- This IP and its component sub-blocks, may be tailored for specific system implementation requirements as part of a design services engagement with Adesto and/or may be optimally integrated with Adesto’s broad portfolio of AFE Building Block IP
- The IAMP can be cost-effectively ported across foundries and process nodes upon request
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- PLC, G.hn, G.Fast Communications
- Multi-mode and multi-band wireless/wireline systems
- Customizable for various wireless/wireline applications
Block Diagram of the 210MHz Differential Current Amplifier IP Core