This PGA has been designed for use as a low noise, programmable gain amplifier for the G.Fast DSL protocol standard.
The PGA has a gain range of -17dB to +22dB. The first stage has a gain range of -17dB to +19dB in 3dB steps. The second stage has a gain range of 0dB to +3dB in 1dB steps. The PGA has a differential input resistance of 400 Ohms, independent of gain setting. The PGA input common-mode is biased at 1.5V to enable maximum input voltage swing. The input impedance and input common-mode are also defined in power-down mode to provide a known termination impedance in the system and also for increased reliability in the presence of large input signal swings. The PGA output common-mode is 0.55V to allow for easy interface to ADC circuitry.
The PGA has DC Offset Correction DAC (6-bit) to minimise the DC offset at the input of the ADC and maximise the ADC input dynamic range.
The PGA has an integrated RC calibration circuit to ensure the pole locations are within +/- 10%.
- TSMC 40nm LP CMOS process
- Bandwidth selectable up to 210MHz
- Fully differential architecture for noise immunity
- Distortion-limited MTPR : 64dB (@ max gain, Narrow Band Mode)
- Noise-limited MTPR: 57dB (@0dB, Narrow Band Mode)
- Integrated RC calibration circuit to ensure pole locations within +/- 10%
- Gain range: -17 to +22dB (1dB gain step)
- DC offset correction
- +/- 1% FS offset
- Low Power Dissipation
- Compact Die Area
- This block has a narrowband and wideband power mode.
- This is intended for combination with S3 Semi's wide portfolio of AFE components and for reconfiguration to a customer's particular requirements
- This IP and its component sub-blocks, may be tailored for specific system implementation requirements as part of a design services engagement with S3 Group and/or may be optimally integrated with S3 Semi's broad portfolio of AFE Building Block IP.
- The PGA can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- PLC, G.hn, G.Fast Communications
- Multi-mode and multi-band wireless/wireline systems
- Customizable for various wireless/wireline applications
Block Diagram of the 210MHz Differential PGA IP Core