This PGA has been designed for use as a low noise, programmable gain amplifier for the G.Fast DSL protocol standard.
The PGA has a gain range of -17dB to +22dB. The first stage has a gain range of -17dB to +19dB in 3dB steps. The second stage has a gain range of 0dB to +3dB in 1dB steps. The PGA has a differential input resistance of 400 Ohms, independent of gain setting. The PGA input common-mode is biased at 1.5V to enable maximum input voltage swing. The input impedance and input common-mode are also defined in power-down mode to provide a known termination impedance in the system and also for increased reliability in the presence of large input signal swings. The PGA output common-mode is 0.55V to allow for easy interface to ADC circuitry.
The PGA has DC Offset Correction DAC (6-bit) to minimise the DC offset at the input of the ADC and maximise the ADC input dynamic range.
The PGA has an integrated RC calibration circuit to ensure the pole locations are within +/- 10%.