In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring, TSMC 12FFC
25G Multi Rate SerDes PHY - TSMC 28nm HPC+
A single SerDes PHY block can consist of up to 16 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 1.25 to 20Gbps. Multiple PHY blocks can be combined to construct wider links. Higher line rates up to 25Gbps can be supported on request.
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