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25G Multi Rate SerDes PHY - TSMC 28nm HPC+
EXTOLL’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are employed to achieve robust performance across process and operating conditions. This allows a maximum of flexibility and reduces the effort for migration to alternate target technologies. The design itself is complemented by the comprehensive advanced verification and modeling methodology employed by EXTOLL.
A single SerDes PHY block can consist of up to 16 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 1.25 to 20Gbps. Multiple PHY blocks can be combined to construct wider links. Higher line rates up to 25Gbps can be supported on request.
A single SerDes PHY block can consist of up to 16 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 1.25 to 20Gbps. Multiple PHY blocks can be combined to construct wider links. Higher line rates up to 25Gbps can be supported on request.
Features
- Line rates from 2.5 up to 25Gbps
- PCIe up to Gen4.0
- PIPE interface
- Ethernet 10G, 25G, 50G, 100G
- JESD204B/C
- SATA up to rev 3.0
- Infiniband up to FDR
- Programmable transmitter with equalizer
- Programmable RX linear equalizer
- Programmable RX DFE
- Digital high speed PLL
- Pattern Generator for diagnostics
- Concurrent Eye Monitor for equalization and channel analysis
- Far End and Near End Loopbacks
- Analog testbus
Deliverables
- Front- and backend integration views
- LIB, LEF, GDSII layout
- Fast Verilog simulation models
- IBIS/AMI models
- PIPE interface RTL
- Documentation
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