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H.264 Baseline Encoder with compressed reference frame store
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25Gbit/s Ethernet PCS
The Chevin Technology 25GPCS provides Ultra low-latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. Ultra-low latency is achieved by using only the PMA function in FPGA Multi-Gigabit transceivers, and moving all PCS functions to code that is optimized for 25GBASE-R. This allows the data to take the shortest and lowest latency path, to and from the wire. The 25GPCS /PMA core can be used directly with Multi-Gigabit Transceivers (SerDes & CDR logic) in Xilinx Virtex® UltraScale FPGAs for the lowest possible latency.
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Block Diagram of the 25Gbit/s Ethernet PCS IP Core
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