The Cadence® 25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 7nm is a high-performance SerDes operating from 1.25 to 25Gbps specifically designed for infrastructure and datacenter applications. It features long reach equalization capability at very low active and standby power. The SerDes offers very low latency for time critical application for enterprise-level data communications, networking, and storage systems.
The PHY IP provides extensive flexibility to mix and match protocols within the same macro. The PHY IP is designed to simultaneously run PCIe®, CCIX, USB, SATA, 10G-KR, XAUI/RXAUI, and SGMII on a per lane basis. Multiple test features are embedded and easily accessible by the end-user. A user-friendly graphical interface called EyeSurfTM provides convenient access to real-time and non-destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic.