The Rambus 28 Gbps Multi-Protocol SerDes (MPS) PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling environments typical of networking and server systems. With high performance and multi-protocol compatibility, the PHYs support data rates from 1.25Gbps to 28.1Gbps across copper and backplane channels with more than 30dB channel insertion loss in a wide range of industry-standard interconnect protocols. They feature application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation. The 28G MPS are designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today's most challenging system environments and applications. This makes the PHYs ideal for many long-reach, copper and backplane enterprise environments.
Features
- Optimized for low-power operation and north/south die-edge placement
- Duplex Lane configurations of x4 and x1
- Adaptive receive equalizer with programmable settings providing up to 12dB of CTLE and 8-tap DFE support
- An LC-PLL provides a wide range of operating frequencies
- Embedded microcontroller for improved system configuration loadsWide range programmable multipliers for reference clock multiplicationPHY is spec compliant across a wide operating junction temperature range (-20 °C to 125 °C). PLLs, bias circuits, and data path are functional between -40 °C to -20 °CBuilt-in Self Test (BIST) supportBuilt-in PRBS15/31 and custom pattern generation and checking for standalone testing
Benefits
- Multi-protocol PHYs supporting data rate in the range of 1.25 Gbps - 28.1 Gbps
- Optimized for low-power operation and north/south die-edge placement
- AC-coupled RX front end with on-chip capacitors
- Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
- Duplex Lane configurations of x4 and x1
- An LC-PLL provides a wide range of operating frequencies
- Wide range programmable multipliers for reference clock multiplication
- Differential reference clock inputs are selectively sourced from C4 or internal ASIC interface pins
- Flexible ASIC clocking
- Programmable clock outputs from the PLL to the ASIC core
- Parallel data, transmitted to the PMA, is synchronous to the transmit parallel data clock from the ASIC core
- Tight lane skew control in the PMA
- Adaptive receive equalizer with programmable settings providing up to 12dB of CTLE and 8-tap DFE support
- Support transmit FIR adaptation through back channel for Ethernet applications
- Built-in Self Test (BIST) support
- At-speed functional test capability with low-speed reference clocks
- Built-in PRBS15/31 and custom pattern generation and checking for standalone testing
- Internal serial loopback with optional phase advancing
- Parallel loopback supported within the PMA
- In-situ real-time monitoring and receive data eye schmoo through an adaptive receive sampler
- ATPG Mux Scan support for digital logic
- IEEE 1149.6 JTAG boundary scan for serial link pins
- Multiple interfaces for the access of PMA registers
- Provides direct register control of all PMA functionality, as well as extended features
- Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
- Optional MDIO interface can be provided as required for Ethernet standard PHYs
- PHYs are spec compliant across a wide operating junction temperature range (-20 °C to 125 °C). PLLs, bias circuits, and data path are functional between -40 °C to -20 °C
- A complete design kit for fast SoC integration
Deliverables
- PMA Hard Macro
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Applications
- Automotive,Communications,Consumer Electronics,Data Processing,Industrial and Medical,Military/Civil Aerospace,Others
Block Diagram of the 28G Multi-protocol SerDes PHY IP Core