SerDes PMA is silicon proven IP offers in TSMC 16nm and 12nm processes. Highline features include excellent insertion loss handling for commuication applications; high-performance supply noise immunity for SoC integration; Build-in Analog calibration for handling process variation; on-chips diagnosis i.e. Loop back testing, PRBS Checker, eye margin monitor, and analog test point monitors ready for chip production.
- TSMC 16/12nm process
- Area & Power: Please contact us
- Package: flip chip BGA
- 16-bits TX/RX digital interface
- Compliant with OIF-CEI-28G-SR/MR standards
- On chip eye monitor
- Automatic calibration of analog circuits
- PRBS loopback test
- APB3.0 bus for management registers
- Technology operates from 10G to 30G wide data rate range.
- Excellent insertion loss handling for enterprise class backplane and optical applications.
- High-performance supply noise immunity for SoC integration.
- Build-in Analog calibration for handling process variation.
- On-chip diagnosis i.e. Loop back testing, PRBS Checker, eye margin monitor, and analog test point monitors ready for chip production.
- Verilog Model
- LEF view
- Timing Libraries
- ATPG Model & Netlist
- Spice Netlist
- Usage Guide and Documentation
- Free Integration Review
- High speed wireline communication