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28Gbps, MR ,SerDes IP ,TSMC 28nm
Credo is the world leading SerDes Technology Company offers silicon proven SerDes IP from “1.25G to 30G” data rate. SerDes PMA is silicon proven IP offers in TSMC 28nm process. Highline features include excellent insertion loss handling for commuication applications; high-performance supply noise immunity for SoC integration; Build-in Analog calibration for handling process variation; on-chips diagnosis i.e. Loop back testing, PRBS Checker, eye margin monitor, and analog test point monitors ready for chip production.
Features
- TSMC 28nm process
- Area & Power: Please contact us
- Package: flip chip BGA
- 16-bits TX/RX digital interface
- Separate RX & TX Macro
- 156.25 or 312.5 Mhz Reference Clock
- Compliant with OIF-CEI-11G-SR/MR standards
- On chip eye monitor
- Automatic calibration of analog circuits
- PRBS loopback test
- APB3.0 bus for management registers
Benefits
- Credo is the only company in the world has the 25G silicon proven SerDes IP in TSMC 28nm process complaints with “CEI-25G-LR” and “CEI-28G-SR” standard.
- 25G SerDes Technology operates from 10G to 30G wide data rate range.
- Excellent insertion loss handling for enterprise class backplane and optical applications.
- High-performance supply noise immunity for SoC integration.
- Build-in Analog calibration for handling process variation.
- On-chip diagnosis i.e. Loop back testing, PRBS Checker, eye margin monitor, and analog test point monitors ready for chip production.
Deliverables
- Verilog Model
- LEF view
- Timing Libraries
- ATPG Model & Netlist
- GDS
- Spice Netlist
- Usage Guide and Documentation
- Free Integration Review
Applications
- High speed wireline communication
Block Diagram of the 28Gbps, MR ,SerDes IP ,TSMC 28nm
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