English
You are here:
2D FIR Filter
The 2D FIR Filter IP core performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory. Its flexible architecture supports a wide variety of filtering operations on various Lattice device families. The highly parameterized design takes advantage of the embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either streaming or bursty input video data. Coefficients may be set at compile time, or updated in system via a simple memory interface.
View 2D FIR Filter full description to...
- see the entire 2D FIR Filter datasheet
- get in contact with 2D FIR Filter Supplier
Block Diagram of the 2D FIR Filter IP Core
FPGA IP
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Embedded FPGA cores in TSMC 22ULP/28HPC/HPC+
- CXL 2.0 Dual Mode Controller
- MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
- DVB-S2 LDPC Decoder and Encoder