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Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
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3.25 Gigabit SerDes
The MXL-SRDS-3204 is a Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 3.2Gbps. It is compatible with router-backplane links, PCI Express, 10 Gbps Ethernet (XAUI), Fibre Channel, SFI-5, SPI-5, Infiniband, and other communication applications. The frequency synthesizing PLL is fully integrated including the loop filter, and has a programmable multiplication factor (4, 5, 8, 10, 16, and 20). Each transmitter accepts an 8 or 10-bit parallel data, serializes it, and outputs the serial data differentially. Each receiver accepts serial differential data at up to 3.2Gbps, recovers the clock and data, de-serializes the data, and makes the data available at the parallel bus.
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Block Diagram of the 3.25 Gigabit SerDes IP Core
SERDES IP
- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- 125Mbps to 16Gbps Multi-protocol SerDes PMA
- 250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency