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3.3 V, 675 Mhz LVDS Transmitter
LVDS33_TX_CUP belongs to S_GPI_IO_T065GP, which is Sankalp’s General Purpose IO library in 65nm TSMC G+ process single poly 9M. It is a LVDS transmitter which operates on 3.3 V supply, at frequencies upto 675MHz (1350Mbps). Power supply sequencing independent (PSSI), Wire bond & Flip chip compatible are some of the salient features for this cell. Cell dimensions are 75um x 210um.
Features
- 1.0 V and 2.5 V devices overdriven to save mask cost
- Operates at frequencies up to 675MHz or 1350Mbps
- Core supply of either 1.0 V or 1.1 V (+/- 10%)
- I/O supply of 3.3 V (+/- 10%)
- Operates over temperature range of -40C to 125C
- ESD hardness of 2kV HBM ,500V CDM
- Latchup immune upto +/- 100mA current injection
- Wire-bond and Flip-chip compatible
- Programmable weak pull-down
- Supports 8-layer (602) or 9-layer (702) metallization with Circuit-Under-Pad (CUP)
- One I/O supply power/ground pair per 2 TX
- Power supply sequence independent (PSSI)
- Compatible to IEEE 1596.3-1996 specification
- Compatible ANSI TIA/EIA-644 specifications
Benefits
- Services Available with this Product
- Customization
- SOC Integration
- Application & ESD Guidance
- Signal Integrity Analysis & Guidelines
- Characterization Support
Deliverables
- Specifications
- GDSII
- LEF
- LVS netlist
- Verilog Model
- Timing Model
- Documentation
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IO
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- LDO Capless Fast Response Series ( Vin = 1.65-1-95V; Vo = 0-75-1.0V; Io = 150 mA ) - TSMC 28nm
- High voltage analog IO pads
- Low Leakage Analog IO Pads