MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
3.3V 100MHz Oscillator IO Inline Pad Set
The 22nm libraries are available in inline and staggered CUP wire bond implementations with a flip chip option.
To utilize these cells in the pad ring, an additional library is required – 3.3V Support: Power. That library contains the DVDD/DVSS power cells necessary for ESD protection, the POC and VREF cells, and a rail splitter to isolate the oscillator in its own power domain as recommended. It also contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. The rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
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ESD IP
- on-chip ESD protection
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- High-voltage solutions in baseline GlobalFoundries and multi-foundry technologies
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