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3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process
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Interface Solution IP
- Northwest Logic AXI Interface Core from Rambus
- Controller IP for PCIe 2.1 as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification
- Controller IP for PCIe 6.0, Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with Native User Interface
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- Common Public Radio Interface (CPRI) v.7.0 IPC
- D2D Controller IP (Die-to-Die Interface)